1. Field of the Invention
The present invention relates to semiconductor memories in general and, more particularly, to an improved dynamic random access memory (DRAM) and method for making such a DRAM wherein a cross-shaped active area enables cells of the DRAM to be packed more densely, reducing memory cell size.
2. Background of Related Art
Random access memory (“RAM”) cell densities have increased dramatically with each generation of new designs and have served as one of the principal technology drivers for ultra large scale integration (“ULSI”) in integrated circuit (“IC”) manufacturing. However, in order to accommodate continuing consumer demand for integrated circuits that perform the same or additional functions and yet have a reduced size as compared with available circuits, circuit designers continually search for ways to reduce the physical size of the memory arrays within these circuits without sacrificing array performance.
While device density is, of course, limited by the resolution capability of available photolithographic equipment, it is also limited by the configuration of the individual memory cells used to make the memory ICs, and the corresponding areas of the memory cells. Conventional memory device arrays include word lines running generally in parallel along one direction and bit line pairs running generally in parallel along a perpendicular direction. The memory cell includes a charge storage structure connected by a transistor to a bit line contact of one of the bit line pairs. Each transistor is activated by a word line. A row of memory cells is selected upon activation of a word line. The state of each memory cell in the row is transferred to a bit line for sensing by sense amplifiers, each of which is connected to a pair of bit lines. The memory cell transfer transistors are formed in the substrate in a plurality of continuous active areas running generally in parallel to each other. A word line forms the gate of the transistor. The transistor formed in the active area provides the pass gate that is controllable to electrically connect the charge storage structure to a bit line. Thus, for example, activation of a word line will cause stored charges to be transferred by corresponding transistors to bit lines. The bit lines are electrically connected to a node of the transistor by bit line contacts.
The area required for each memory cell in a memory array partially determines the capacity of a memory IC. This area is a function of the number of elements in each memory cell and the size of each of the elements. For example, FIG. 1A illustrates an array 100 of memory cells 110 for a conventional dynamic random access memory (DRAM) device. Memory cells 110 are typically formed in adjacent pairs, where each pair of cells is formed in a common active area 120 and share a common source/drain region that is connected to a respective digit line via a digit line contact 124. The area of the memory cells 110 is said to be 8F2, where F represents a minimum feature size for photolithographically defined features. For conventional 8F2 memory cells, the dimension of the cell area is 2F×4F. The dimensions of a conventional 8F2 memory cell are measured along a first axis from the center of a shared digit line contact 124 (½F), across a word line 128 that represents an access transistor (1F), a storage capacitor 132 (1F), an adjacent word line 136 (1F), and half of an isolation region 140 (½F) separating the active area 120 of an adjacent pair of memory cells (i.e., resulting in a total of 4F). The dimensions along a second perpendicular axis are half of an isolation region 150 on one side of the active area 120 (½F), the digit line contact 124 (1F), and half of another isolation region 154 on the other side of the active area 120 (½F) (i.e., resulting in a total of 2F).
In some state-of-the-art memory devices, the memory cells for megabit DRAM have cell areas approaching 6F2. FIG. 1B illustrates aligned memory cells used to form a DRAM wherein all memory cells along a word line are simultaneously accessed and the area of each memory cell 101 is 3F×2F=6F2. The 6F2 memory cell 101 illustrated has an open digit line array architecture. In FIG. 1B, a box is drawn around the memory cell 101 or memory bit to show the cell's outer boundary. As shown in more detail in FIG. 1C, along the horizontal axis of the memory cell 101, the box includes one-half digit line contact feature 102 (½F), one word line feature 104 (1F), one capacitor feature 106 (1F), and one-half field oxide feature 108 (½F), totaling three features. Along the vertical axis of the memory cell 101, the box contains two one-half field oxide features 112, 114 (½F, ½F) and one active area feature 116 (1F), totaling two features such that the structure of the memory cell 101 results in its area being 3F×2F=6F2. A digit line 105 passes through the active area, orthogonally to word line 104.
Although this 6F2 memory cell offers an approximately 25% improvement in memory cell area relative to conventional 8F2 memory cells, as previously described, a further reduction in memory cell size is still desirable. Memory arrays having memory cell areas approaching 4F2 require novel devices and are, therefore, more expensive to fabricate. Additional equipment and processing steps drive up the costs of conventional 4F2 memory cells. Therefore, there is a need for a still more compact memory cell structure and method for forming the same.
Accordingly, the inventor has recognized the need for a high performance DRAM which includes more memory cells within the same area of DRAM real estate.